PXIe-6674T NI

接口与扩展性

-前端连接器:

-6个SMA接口(PFI 0-5),支持单端LVTTL或LVDS差分模式;

-3对PFI_LVDS(可编程输入/输出,不兼容同时双向传输);

-多机箱同步:

-通过PXIe_DSTARA/B/C实现跨PXI/PXI Express机箱信号互联。

兼容性与安装要求

-机箱适配:

-需安装于PXI Express机箱的系统时钟槽(部分机箱支持其他插槽,但部分功能受限);

-兼容PXI与PXI Express混合系统;

-驱动支持:

-最低支持NI-Sync 3.4.1驱动,推荐使用最新版本。

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描述

产品概述

PXIe-6674T是美国国家仪器(NI)推出的高性能PXI Express时钟与同步模块,专为多设备高精度同步、复杂触发场景设计。其集成板载精密控温晶体振荡器(OCXO)与直接数字合成(DDS)技术,支持跨机箱信号路由,适用于高通道数测量系统(如半导体测试、航空航天设备监测)。

核心功能与特性

时钟生成与同步

-高精度参考源:

-板载OCXO(精度80 ppb),输出稳定10 MHz时钟;

-DDS电路生成0.3 Hz至1 GHz可编程时钟(分辨率2.84µHz);

-信号路由:

-支持CLKIN/CLKOUT配置,可连接外部时钟或PXI_CLK10_IN;

-差分LVDS触发总线(PXIe_DSTARA/B/C)及8条PXI触发线。

接口与扩展性

-前端连接器:

-6个SMA接口(PFI 0-5),支持单端LVTTL或LVDS差分模式;

-3对PFI_LVDS(可编程输入/输出,不兼容同时双向传输);

-多机箱同步:

-通过PXIe_DSTARA/B/C实现跨PXI/PXI Express机箱信号互联。

兼容性与安装要求

-机箱适配:

-需安装于PXI Express机箱的系统时钟槽(部分机箱支持其他插槽,但部分功能受限);

-兼容PXI与PXI Express混合系统;

-驱动支持:

-最低支持NI-Sync 3.4.1驱动,推荐使用最新版本。

技术参数

|参数类别|详细规格|

|时钟性能|DDS频率范围:0.3 Hz–1 GHz;OCXO稳定性:±80 ppb|

|触发线路|8条双向PXI触发线+13组差分PXIe_DSTAR触发对|

|物理接口|6×SMA单端/LVDS可配置接口+3×LVDS差分对|

|功耗与散热|典型功耗<15 W(需参考机箱散热设计)|

典型应用场景

高密度数据采集:

-协调多块PXIe-6363动态信号采集卡同步采样(如振动台多点监测);

分布式测试系统:

-跨机箱同步PXIe-6674T与第三方仪器(如示波器、逻辑分析仪);

精密触发控制:

-实现半导体测试中的多阶段触发序列(如电源启动与信号捕获联动)。

Product Overview

The PXIe-6674T is a high-performance PXI Express clock and synchronization module launched by National Instruments(NI),designed for high-precision synchronization and complex trigger scenarios for multiple devices.It integrates on-board precision temperature-controlled crystal oscillator(OCXO)and direct digital synthesis(DDS)technology,supports cross-chassis signal routing,and is suitable for high-channel number measurement systems(such as semiconductor testing,aerospace equipment monitoring).

Core functions and features

Clock generation and synchronization

-High-precision reference source:

-Onboard OCXO(precision 80 ppb),stable output of 10 MHz clock;

-DDS circuit generates a programmable clock from 0.3 Hz to 1 GHz(resolution 2.84µHz);

-Signal routing:

-Supports CLKIN/CLKOUT configuration,can be connected to external clock or PXI_CLK10_IN;

-Differential LVDS trigger bus(PXIe_DSTARA/B/C)and 8 PXI trigger lines.

Interface and Extensibility

-Front-end connector:

-6 SMA interfaces(PFI 0-5),supporting single-ended LVTTL or LVDS differential mode;

-3 pairs of PFI_LVDS(programmable input/output,incompatible with simultaneous bidirectional transmission);

-Multi-chassis synchronization:

-Achieves cross-PXI/PXI Express chassis signal interconnection through PXIe_DSTARA/B/C.

Compatibility and installation requirements

-Chassis adaptation:

-The system clock slot that needs to be installed in the PXI Express chassis(some chassis supports other slots,but some functions are limited);

-Compatible with PXI and PXI Express hybrid systems;

-Driver support:

-The minimum support for NI-Sync 3.4.1 driver is recommended.The latest version is recommended.

Technical parameters

|Parameter category|Detailed specifications|

|Clock performance|DDS frequency range:0.3 Hz–1 GHz;OCXO stability:±80 ppb|

|Trigger line|8 bidirectional PXI trigger lines+13 differential PXIe_DSTAR trigger pairs|

|Physical Interface|6×SMA Single-ended/LVDS Configurable Interface+3×LVDS Differential Pair|

|Power and heat dissipation|Typical power dissipation<15 W(refer to the chassis heat dissipation design)|

Typical application scenarios

High-density data acquisition:

-Coordinate the synchronous sampling of multiple PXIe-6363 dynamic signal acquisition cards(such as multi-point monitoring of the vibration table);

Distributed testing system:

-Synchronize PXIe-6674T with third-party instruments(such as oscilloscopes,logic analyzers)across chassis;

Precision trigger control:

-Implement multi-stage trigger sequences in semiconductor testing(such as linkage of power start and signal capture).